Semi-Hermetic-507718 Each node (VMIxxx-5565 Reflective Memory boards) in the network is interconnected using fiber-optic cables in a daisy chain loop. The transmitter of the first board must be tied to the receiver of the second board. The transmitter of the second board is tied to the receiver of the third, and so on, until the loop is completed back at the receiver of the first board. Each node must have a unique node ID, which is accomplished using a bank of eight (8) onboard jumpers. The order of the node IDs is unimportant; they just have to be unique (i.e. no two nodes can have the same node ID). A transfer of data over the network is initiated by a write to onboard SDRAM from the PCI host system. The write can be as simple as a PCI target write, or it can be due to a DMA cycle by one of the two resident DMA engines. When the write to the SDRAM is occurring, circuitry on the VMIPCI-5565 automatically writes the data, along with other pertinent information, into the transmit FIFO. From the transmit FIFO, a transmit circuit retrieves the data and forms it into variable length packets of from 4 to 64 bytes, which pass over the fiber-optic interface to the receiver of the next board. When data is received, a circuit opens the packets and stores the data in the board’s receive FIFO. From the receive FIFO, a third circuit writes the data into local onboard SDRAM at the same relative location in memory as that of the originating node. The third circuit also simultaneously routes the data into the board’s own transmit FIFO. From there, the process is repeated until the data returns to the receiver of the originating node. At the originating node, the data packet is removed from the network. Front Bezel LED Indicators The VMIPCI-5565 has three LED indicators located on the bezel. The top red LED is a status indicator, its power up default state is “ON”. The status LED may be toggled “OFF” or “ON” by writing to a bit (Bit 31 of the Control and Status register), which indicates a user defined board status. The middle yellow LED is the signal detect indicator. The signal detect LED turns “ON” if the receiver detects light. It can be used as a simple method of checking that the optical network is properly connected to the receiver. The bottom green LED is the OWN DATA indicator. When a board detects its own data returning on the network, it sets this LED “ON”. Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com 23 VMIPCI-5565 Register Sets 1 VMIPCI-5565 Register Sets To go beyond the simple target read and write operation of the board, the user must understand and manipulate bits within five register sets. The five register sets are referred to as: • PCI Configuration Registers • Local Configuration Registers • Runtime Registers • DMA Control Registers • Reflective Memory (RFM) Control and Status Registers PCI Configuration Registers – This set of registers is predefined by the PCI Local bus Specification and is standard for all PCI devices. This register set contains the Vendor ID, Device ID, Subsystem Vendor ID, Subsystem ID and Base Address registers. The PCI Configuration Registers are first initialized by a serial EEPROM and then modified as needed by the PCI bus system BIOS. The register set is rarely altered by the user. Local Configuration Registers – This set of registers resides in the PLX PCI interface device. Like the previous set of registers, the Local Configuration registers are also initialized to a normal operating configuration from a serial EEPROM. Occasionally, a user may wish to modify a Local Configuration Register to better match the VMIxxx-5565 to the host system at start up. After that, the Local Configuration Register settings are seldom modified. The starting location of the Local Configuration Registers is defined in the PCI Configuration Registers, Base Address Register 0 and/or Base Address Register 1. Runtime Registers – This set of registers is actually a subset of the Local Configuration Registers and is accessed at locations offset from the value in the Base Address Registers 0 or 1. Unlike the other registers, the Runtime Registers frequently change during operation. One significant register in this register set is the PLX Interrupt Control and Status register (INTCSR). DMA Control Registers – This register set, like the Runtime Registers, is actually a subset of the Local Configuration Registers and is accessed at locations offset from the value in Base Address Registers 0 or 1. The DMA Control Registers are used to operate the two DMA engines. Reflective Memory (RFM) Control and Status Registers – Unlike the previous four register sets, the RFM Control and Status Registers do not reside in the PLX PCI interface device but, rather are located in additional board circuitry. The RFM Control and Status Registers implement the functions unique to the VMIxxx-5565 Reflective Memory board. These functions include RFM operation status, detailed control of the RFM sources for the PCI interrupt, and network interrupt access. The RFM Control and Status Registers are accessed at locations offset from the value in Base Address Register 2 (PLX also refers to this address space as “Local Address Space 0”). Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com 24 1 VMIPCI-5565 Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts Reflective Memory RAM The actual onboard Reflective Memory SDRAM is available in two sizes: 64MB or 128MB with parity. The SDRAM starts at the location specified in Base Address Register 3 (PLX refers to this address space as “Local Address Space 1”). Unlike the previous versions of GE Fanuc Embedded Systems’ Reflective Memory products, the RFM Control and Status Registers do NOT replace the first $40 locations of RAM. The offset address range is $0 to $3FFFFFF for the 64MB option, or $0 to $7FFFFFF for the 128MB option. Parity Function The parity function is not enabled at power up and must be enabled by setting bits 0, 6 and 7 in the Local Configuration Register’s INTCSR at offset $68, and also by setting Bit 13 in the RFM Control and Status Register’s Local Interrupt Enable (LIER) register at offset $14. To use the parity function, writes must occur on 32-bit (Lword) or 64-bit (Qword) boundaries. While parity is active, 8-bit (byte) writes and 16-bit (word) writes are prohibited. In addition, since the RAM does not power up in a valid parity state, any location that is to be read with parity must first be initialized by a write of some data pattern. Otherwise the read will assert an erroneous parity error. Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com 25 Interrupt Circuits 1 Interrupt Circuits The VMIPCI-5565 has a single PCI interrupt output (INTA#). One or more events on the VMIPCI-5565 can cause the interrupt. The sources of the PCI interrupt can be individually enabled and monitored through several registers. The interrupt circuitry of the VMIPCI-5565 is arranged in two tiers. The first tier of interrupts are enabled and monitored in the PLX device by the Local Configuration Register’s INTCSR register at offset $68. The optional sources for monitoring of the first tier interrupts include: 1. Local-to-PCI Doorbell register 2. Messaging Outbound Post Queue not empty 3. Master/Target Abort Status condition 4. 256 consecutive PCI Retries as PCI bus master 5. DMA Ch 0 Done/Terminal Count 6. DMA Ch 1 Done/Terminal Count 7. Local Interrupt Input (LINTi#) The first tier sources (1) and (2) listed above have limited use in the VMIPCI-5565. The first tier sources (3) and (4) are used at the discretion of the host system requirements. The first tier sources (5) and (6) are used during DMA cycles and must be further configured in the DMA registers. The final first tier interrupt source (7) is the Local Interrupt Input (LINTi#). The LINTi# signal is an actual physical input to the PLX device and is significant due to the fact that all secondary tier interrupts are funneled through the LINTi#. Second tier interrupts include several operational faults and four network interrupts. The second tier interrupts are selected and monitored through the two RFM Control and Status Registers referred to as the Local Interrupt Status Register (LISR) and the LIER. For a detailed description of the two registers refer to the Programming section. A block diagram of the main interrupt circuitry is shown in Figure 1-1 on page 26. Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com 26 1 VMIPCI-5565 Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts Figure 1-1 VMIPCI-5565 Interrupt Circuitry Block Diagram Network Receiver Circuitry Network Interrupt FIFO's 4 Local Interrupt Status Register (LISR) (Offset $10) Local Interrupt Enable Register (LIER) (Offset $14) RFM Control and Status Registers RFM Fault/Status Events + LSERR# LINT# Bits 0, 6 and 7 (Local Parity) Interrupt Control and Status Register (Offset $68) Bits 11 and 15 DMA 0 DMA 1 Bits 18 and 21 Bits 19 and 22 PLX Runtime Registers PCI Interrupt (INTA#) Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com 27 Interrupt Circuits 1 Network Interrupts The VMIPCI-5565 has the capability of passing interrupts packets over the network in addition to data. The network interrupt packets can be directed to a specific node or broadcast globally to all nodes on the network. Each network interrupt packet contains the sender’s node ID, the target (destination) node ID, the interrupt type information and 32 bits of user defined data. The types of network interrupts include three (3) general purpose interrupts, a network initialized interrupt and a reset node request interrupt. The sending node specifies the target (destination) node, the interrupt type and 32 bits of data using three RFM Control and Status registers. Each receiving node evaluates the interrupt packets as they pass through. If the interrupt is directed to that node, then the sender’s node ID is stored in the appropriate Sender ID FIFO (one of four). The Sender ID FIFO is 127 locations deep. The data will be stored in a companion 127 locations deep data FIFO. If enabled through the LISR, LIER and INTCSR registers, any of the four possible network interrupts can also generate a host PCI interrupt at each receiving node. The network initialized interrupt is much like one of the three general purpose interrupts and can be used as a fourth general purpose interrupt if desired. However, it does have an additional function. When a VMIPCI-5565 is initialized due to power up or a reset, the local processor can generate a network initialized interrupt globally to all other nodes on the network. This event can be used to inform the host system or another (master) node that some portion of the memory on that node needs to be re-initialized. The reset node request interrupt is not stored in a FIFO like the other four network interrupts. Furthermore, it does not cause an immediate reset of the board. Instead, it can only set a bit in the LISR register, which will result in a PCI interrupt if enabled. The actual board reset should be performed by the host system in an orderly fashion. Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com 28 1 VMIPCI-5565 Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts Redundant Transfer Mode of Operation The VMIPCI-5565 is capable of operating in a redundant transfer mode. The board is configured for redundant mode when the jumper shunt between pins 1 and 2 of jumper E7 is removed. While in the redundant transfer mode, each packet will be transferred twice, regardless of the dynamic packet size. The receiving circuitry of each node on the network evaluates each of the redundant transfers. If no errors are detected in the first transfer, it is used to update the onboard memory and the second transfer is discarded. However, if the first transfer does contain an error, the second transfer is used to update the onboard memory provided it has no transmission errors. If errors are detected in both transfers, the transfers will not be used and the data is completely removed from the network. Statistically, redundant transfer mode greatly reduces the chance that any data is dropped from the network. However, the redundant transfer mode also reduces the effective network transfer rates. The single Lword (4 byte) transfer rate drops from the non-redundant rate of 47.1MB/s to approximately 20MB/s. The 16 Lword (64 byte) transfer rate drops from the non-redundant rate of 174MB/s to the redundant rate of 87MB/s. Rogue Packet Removal Operation A rogue packet is a packet that does not belong to any node on the network. Recalling the basic operation of Reflective Memory, one node originates a packet on the network in response to a memory write from the host. The packet is transferred around the network to all nodes until it returns to the originating node. It is then a requirement of the originating node to remove the packet from the network. If, however, the packet somehow gets altered as it passes through another node or if the originating node begins to malfunction, then the originating node may fail to recognize the packet as its own and will not remove the packet from the network. In this case, the packet will continue to traverse the network. Rogue packets are extremely rare. Their existence indicates a malfunctioning board due to true component failure, or due to operation in an overly harsh environment. Normally, the solution is to isolate and replace the malfunctioning board and/or improve the environment. However, some users prefer to tolerate sporadic rogue packets rather than halt the system for maintenance provided the rogue packets are removed from the network. To provide tolerance to rogue packet faults, the VMIPCI-5565 contains circuitry which allows it to operate as one of two Rogue Masters. A rogue master alters each packet as it passes through from another node. If the same packet returns to the rogue master a second time, the Rogue Master recognizes that it is a rogue packet and removes it from the link. When a rogue packet is detected, a rogue packet fault flag is set in the register called the LISR. The assertion of the rogue packet fault bit may optionally assert a PCI interrupt to inform the host that the condition exists. Two rogue masters, Rogue Master 0 and Rogue Master 1, are provided to cross check each other. Rogue Master 0 is enabled by removing the jumper shunt between pins 3 and 4 of jumper block E7. Rogue Master 1 is enabled by removing the jumper shunt between pins 5 and 6 of jumper block E7. Just as two boards in a network should not have the same node ID, two boards in the same network should not be set as the same Rogue Master. Otherwise, one of the two will erroneously remove packets originated by the other. |
