IMG_7619块备件

AS-B809-016

网络中的每个节点（VMIxxx-5565反射存储板）都是互连的
在菊花链回路中使用光纤电缆。一块板的发射器必须：
系在二板的接收器上。二板的发射器被捆扎
到三个的接收器，依此类推，直到循环在接收器处完成
一块板的一部分。每个节点必须具有一的节点ID，这是可以实现的
使用一组八（8）个车载开关。节点ID的顺序不重要；
它们必须是一的（即，没有两个节点可以具有相同的节点ID）。
网络上的数据传输由来自的对板载SDRAM的写入启动
VMEbus主机系统。写入可以像VMEbus写入一样简单，也可以是
由于DMA引擎的循环。当发生对SDRAM的写入时，
上的电路自动写入数据以及其他数据
将相关信息输入到发送FIFO中。从发送FIFO
电路检索数据并将其形成大小从4到64的可变长度数据包
字节，通过光纤接口传输到下一块板的接收器。什么时候
当接收到数据时，电路打开数据包并将数据存储在电路板的接收端
先进先出。三个电路从接收FIFO将数据写入本地板上存储器
SDRAM位于存储器中与始发节点相同的相对位置。这个
三个电路还同时将数据路由到电路板自己的传输FIFO中。
从那里开始，重复该过程，直到数据返回到接收器
始发节点。在始发节点，数据分组从源节点移除
网络
前面板LED指示灯
有三个LED指示灯，位于前面板上。底部
红色LED是一个状态指示器，其通电默认状态为“开”。状态LED可以是
通过写入位（控制和状态的位31）来切换“关闭”或“打开”
寄存器），其指示用户定义的板状态。中间的黄色LED为红色
信号检测指示器。如果接收器检测到光，信号检测LED将点亮。
它可以用作检查光网络是否正常工作的简单方法
连接到接收器。顶部的绿色LED是自己的数据指示器。当
电路板检测到自己的数据在网络上返回，它将此LED设置为“on”。
注意：确保光纤电缆完全连接到接收器，以：
避免了错误。即使电缆部分断开，信号检测LED也将点亮
有联系的。
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23
寄存器组1
寄存器组
要超越电路板的简单读写操作，用户必须：
理解和操作两个寄存器组中的位。这两个寄存器组是：
称为：
•宇宙二号寄存器
•反射存储器（RFM）控制和状态寄存器
Universe II寄存器-这组寄存器是Universe II设备专用控制
以及驻留在VMEbus桥中的状态和DMA控制寄存器。宇宙
控制和状态寄存器便于主机系统配置，并允许用户
以控制VMEbus桥接器操作特性。VMEbus桥寄存器
有一个小的端字节排序。DMA控制寄存器用于操作
DMA引擎。这些寄存器位于与基准偏移0美元的位置。基址是
使用开关S7、S4和S3确定。
反射存储器（RFM）控制和状态寄存器–RFM控制和
状态寄存器实现VMIxxx-5565反射式传感器特有的功能
内存板。这些功能包括RFM操作状态、控制系统的详细信息
用于VMEbus中断和网络中断访问的RFM源。这些寄存器
位于距基地1200美元的位置。使用开关确定基址
S7、S4和S3。
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24
1 带中断的超高速光纤反射存储器
反射存储器RAM
实际的板载反射内存SDRAM有两种尺寸：64 MB
或具有奇偶校验的128兆字节。SDRAM从开关S8指定的位置开始。
与之前版本的VMIC反射式内存产品不同，RFM
控制和状态寄存器不会取代RAM的前40个位置。
奇偶函数
通电时不启用奇偶校验功能，必须通过设置位13来启用
在RFM CSR的本地中断启用（LIER）寄存器中，偏移量为$14。要使用奇偶校验
在函数中，写入必须发生在32位（Lword）或64位（Qword）边界上。虽然
奇偶校验处于活动状态，禁止8位（字节）写入和16位（字）写入。此外
由于RAM在有效奇偶校验状态下不加电
奇偶校验必须首先通过写入某些数据模式来初始化。

AS-B809-016

AS-B809-016

Each node (VMIxxx-5565 Reflective Memory boards) in the network is interconnected using fiber-optic cables in a daisy chain loop. The transmitter of the first board must be tied to the receiver of the second board. The transmitter of the second board is tied to the receiver of the third, and so on, until the loop is completed back at the receiver of the first board. Each node must have a unique node ID, which is accomplished using a bank of eight (8) on-board switches. The order of the node IDs is unimportant; they just have to be unique (i.e. no two nodes can have the same node ID). A transfer of data over the network is initiated by a write to on-board SDRAM from the VMEbus host system. The write can be as simple as a VMEbus write, or it can be due to a cycle by the DMA engine. When the write to the SDRAM is occurring, circuitry on the automatically writes the data, along with other pertinent information, into the transmit FIFO. From the transmit FIFO, a transmit circuit retrieves the data and forms it into variable length packets sizes from 4 to 64 bytes, which pass over the fiber-optic interface to the receiver of the next board. When data is received, a circuit opens the packets and stores the data in the board’s receive FIFO. From the receive FIFO, a third circuit writes the data into local on-board SDRAM at the same relative location in memory as that of the originating node. The third circuit also simultaneously routes the data into the board’s own transmit FIFO. From there, the process is repeated until the data returns to the receiver of the originating node. At the originating node, the data packet is removed from the network. Front Panel LED Indicators The has three LED indicators located on the front panel. The bottom red LED is a status indicator, its power up default state is “ON”. The status LED may be toggled “OFF” or “ON” by writing to a bit (Bit 31 of the Control and Status register), which indicates a user defined board status. The middle yellow LED is the signal detect indicator. The signal detect LED turns “ON” if the receiver detects light. It can be used as a simple method of checking that the optical network is properly connected to the receiver. The top green LED is the OWN DATA indicator. When a board detects its own data returning on the network, it sets this LED “ON”. NOTE: Ensure that the fiber-optic cables are completely connected to the receiver to avoided errors. The signal detect LED will come on even when the cable is partially connected. Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com 23 Register Sets 1 Register Sets To go beyond the simple read and write operation of the board, the user must understand and manipulate bits within two register sets. The two register sets are referred to as: • Universe II Registers • Reflective Memory (RFM) Control and Status Registers Universe II Registers - This set of registers are the Universe II Device Specific Control and Status and DMA Control Registers, residing in the VMEbus bridge. The Universe II Control and Status Registers facilitate host system configuration and allow the user to control VMEbus bridge operational characteristics. The VMEbus bridge registers have little-endian byte-ordering. The DMA Control Registers are used to operate the DMA engine. These registers are located at $0 offset from base. The base address is determined using switches S7, S4 and S3. Reflective Memory (RFM) Control and Status Registers – The RFM Control and Status Registers implement the functions unique to the VMIxxx-5565 Reflective Memory board. These functions include RFM operation status, detailed control of the RFM sources for the VMEbus interrupt, and network interrupt access. These registers are located at $1200 offset from base. The base address is determined using switches S7, S4 and S3. Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com 24 1 Ultrahigh-Speed Fiber-Optic Reflective Memory with Interrupts Reflective Memory RAM The actual on-board Reflective Memory SDRAM is available in two sizes: 64 Mbytes or 128 Mbytes with parity. The SDRAM starts at the location specified by switch S8. Unlike the previous versions of VMIC’s Reflective Memory products, the RFM Control and Status Registers do NOT replace the first $40 locations of RAM. Parity Function The parity function is not enabled at power up and must be enabled by setting Bit 13 in the RFM CSR’s Local Interrupt Enable (LIER) register at offset $14. To use the parity function, writes must occur on 32-bit (Lword) or 64-bit (Qword) boundaries. While parity is active, 8-bit (byte) writes and 16-bit (word) writes are prohibited. In addition, since the RAM does not power up in a valid parity state, any location that is to be read with parity must first be initialized by a write of some data pattern. Otherwise the read will assert an erroneous parity error. Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com 25 Interrupt Circuits 1 Interrupt Circuits The has a single programmable VMEbus interrupt output. One or more events on the can cause the interrupt. The sources of the VMEbus interrupt can be individually enabled and monitored through several registers. The interrupts are selected and monitored through the two RFM CSRs referred to as the Local Interrupt Status Register (LISR) and the Local Interrupt Enable Register (LIER). For a detailed description of the two registers refer to the Programming section. A block diagram of the main interrupt circuitry is shown in Figure 1-1 on page 26. Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com 26 1 Ultrahigh-Speed Fiber-Optic Reflective Memory with Interrupts Figure 1-1 Interrupt Circuitry Block Diagram Network Receiver Circuitry Network Interrupt FIFO's 4 Local Interrupt Status Register (LISR) (Offset $10) Local Interrupt Enable Register (LIER) (Offset $14) RFM Control and Status Registers RFM Fault/Status Events + LINT0 VMEbus Interrupt Enable Register (VINT_EN) (Offset $310) Bit 0 DMA Bit 08 Universe II Registers VMEbus Interrupts (1 thru 7) Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com 27 Interrupt Circuits 1 Network Interrupts The has the capability of passing interrupt packets over the network in addition to data. The network interrupt packets can be directed to a specific node or broadcast globally to all nodes on the network. Each network interrupt packet contains the sender’s node ID, the target (destination) node ID, the interrupt type information and 32 bits of user defined data. The types of network interrupts include four (4) general purpose interrupts. The sending node specifies the target (destination) node, the interrupt type and 32 bits of data using three RFM Control and Status registers. Each receiving node evaluates the interrupt packets as they pass through. If the interrupt is directed to that node, then the sender’s node ID is stored in the appropriate Sender ID FIFO (one of four). The Sender ID FIFO is 127 locations deep. The data will be stored in a companion 127 locations deep data FIFO. If enabled through the LISR, LIER and VINT_EN registers, any of the four possible network interrupts can also generate a host VMEbus interrupt at each receiving node. Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com 28 1 Ultrahigh-Speed Fiber-Optic Reflective Memory with Interrupts Redundant Transfer Mode of Operation The is capable of operating in a Redundant Transfer mode. The board is configured for redundant mode when pins 1 and 2 of jumper E5 has the shunt removed. While in the redundant transfer mode, each packet will be transferred twice, regardless of the dynamic packet size. The receiving node evaluates each of the redundant transfers. If no errors are detected in the first transfer, it is used to update the on-board memory and the second transfer is discarded. If however the first transfer does contain an error, the second transfer is used to update the on-board memory provided it has no transmission errors. If errors are detected in both transfers, the transfers will not be used and the data is completely removed from the network. The Bad Data bit (Bit 01 of the LCSR) will be set if an error is detected in either transfer. Redundant transfer mode greatly reduces the chance that any data is dropped from the network. However, the redundant transfer mode also reduces the effective network transfer rates. The single Lword (4 byte) transfer rate drops from the non-redundant rate of 43 Mbyte/sec. to approximately 20 Mbytes/sec. The 16 Lword (64 byte) transfer rate drops from the non-redundant rate of 174 Mbyte/sec. to the redundant rate of 87 Mbyte/sec. Rogue Packet Remove Operation A rogue packet is a packet that does not belong to any node on the network. Recalling the basic operation of Reflective Memory, one node originates a packet on the network in response to a memory write from the host. The packet is transferred around the network to all nodes until it returns to the originating node. It is then a requirement of the originating node to remove the packet from the network. If, however, the packet somehow gets altered as it passes through another node or if the originating node begins to malfunction, then the originating node may fail to recognize the packet as its own and will not remove the packet from the network. In this case the packet will continue to pass around the network. Rogue packets are extremely rare. Their existence indicates a malfunctioning board due to true component failure or due to operation in an harsh environment. Normally, the solution is to isolate and replace the malfunctioning board and/or improve the environment. However, some users prefer to tolerate sporadic rogue packets rather than halt the system for maintenance provided the rogue packets are removed from the network. To provide tolerance to rogue packet faults, the can operate as one of two rogue masters. A rogue master alters each packet as it passes from one node to another. When the packet returns to the rogue master a second time, the rogue master recognizes that it is a rogue packet and removes it from the ring. When a rogue packet is detected, a rogue packet fault flag is set in the Local Interrupt Status Register (LISR). The assertion of the rogue packet fault bit may optionally assert a VMEbus interrupt to inform the host that the condition exists. Rogue Master 0 and Rogue Master 1, are provided to cross check each other. Rogue Master 0 is enable removing the jumper shunt from E5 pins 3 and 4. Rogue Master 1 is enable by removing the jumper shunt from E5 pins 5 and 6. See “ Location of User Configurable Switches and Jumpers” on page 35. NOTE: Two boards in the network should not be set as the same rogue master. Otherwise, one of the two will erroneously remove packets originated by the other. Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com 29 Byte Ordering: Big Endian / Little Endian 1 Byte Ordering: Big Endian / Little Endian The byte-ordering issue exists due to the different traditions at the major microprocessor manufacturers, Motorola and Intel. VMEbus boards are designed around Motorola’s 680X0 processors and compatibles, which store multiple-byte values in memory with the most significant byte at the lowest byte address. This byte-ordering scheme became known as “Big Endian” ordering. On the other hand, Intel’s 80X86 microprocessors, store multiple-byte values in memory with the least significant byte in the lowest byte address, earning the name “Little Endian” ordering. The ’s PCI-to-VMEbus interface uses an Intel based or equivalent bridge chip, which uses Little Endian byte ordering. Byte arrangement and the byte relationship between data in the processor and transferred data in memory are shown in Figure 1-2. Figure 1-2 Byte Relationships Using the Little Endian Pentium Microprocessor Note that in Little Endian devices, the Memory’s least significant byte is stored in the lowest byte address after a multiple-byte write (such as the Lword transfer illustrated), while the Reflective Memory’s most significant byte is stored in the highest byte address after such transfers. Conversely, the processor considers data retrieved from the lowest byte address to be the least significant byte after a multiple-byte read. Data retrieved from the highest byte address is considered to be the most significant byte. Contrast the behavior of the Little Endian Pentium in Figure 1-2 with the same Lword transfer using a Big Endian processor like the Motorola 68040 in Figure 1-3 on page 30. Note that the Big Endian 68040 handles the same Lword transfer in a completely different manner than the Little Endian Pentium microprocessor. During a multiple-byte transfer like the Lword transfer illustrated, a Big Endian processor writes its least significant byte in the highest byte address in memory, while its most significant byte is written to the lowest address. The converse is true during read operations: the data in the lowest byte address is considered to be the most significant, while the byte in the highest address is considered to be the least significant. D31-D24 D23-D16 D15-D08 D07-D00 MSB LSB Data Within the Pentium Microprocessor BYTE $03 BYTE $02 BYTE $01 BYTE $00 . . . Data Within Memory Lword (32-bit) Transfer MSB LSB Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com 30 1 Ultrahigh-Speed Fiber-Optic Reflective Memory with Interrupts Figure 1-3 Byte Relationships Using the Big Endian 68040 Microprocessor The VMEbus Specification does not specify which byte of a multiple-byte transfer is most significant. The VMEbus Specification does, however, require certain byte lanes to be associated with certain byte addresses. As shown in Table 1-1 on page 31, byte(0) must be transferred on data lines D31-D24 during a Lword transfer while byte(3) must be transferred on lines D7-D0. This byte and address alignment is exactly the same as that for a Big Endian processor such as the Motorola 68040. If a Little Endian device were to have its data bus directly connected to the VMEbus (i.e., D31 to D31, D30 to D30, etc.), then the most significant byte data supplied to the VMEbus D31-D24 byte lane during a Lword write would be stored by the VMEbus in the lowest of the four destination byte addresses – opposite that expected by the Pentium microprocessor. This poses no problem if the 32-bit value written is always read back using a similar Lword transfer (i.e., all four bytes at once), since the swapped data gets swapped again and appears to the Host exactly as it should. However, if the data written by the 32-bit Lword transfer were to be retrieved using any other method, for example, using four separate byte transfers creates a problem. The data at the lowest byte address would be incorrectly assumed to be the least significant, while it is actually the most significant. The problem cannot be solved by simply connecting the to the VMEbus with its byte lanes crossed. For example, the uses D0-D7 to transfer a byte to address $00, while the VMEbus requires D8-D15 be used. For this reason, special hardware has been incorporated into the PCI-to-VMEbus interface to facilitate different kinds of byte swapping for varying circumstances. D31-D24 D23-D16 D15-D08 D07-D00 MSB LSB Data Within the 68040 Microprocessor BYTE $03 BYTE $02 BYTE $01 BYTE $00 . . . DataWithin Memory Lword (32-bit) Transfer MSB LSB Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com 31 Byte Ordering: Big Endian / Little Endian 1 Endian Conversion Hardware The Universe II chip performs Address Invariant translation between the PCI and VMEbus interfaces. Address Invariant mapping or “Non-endian conversion” mode maintains the byte ordering between the two interfaces (i.e. data originating in Little Endian mode on the PCI side will remain in Little Endian mode on the VMEbus side of the interface). However, the PCI-to-VMEbus interface has external endian conversion logic which allows the applicati