00-104-196 Introduction: is the VMEbus member of the GE Fanuc Embedded Systems VMIxxx-5565 family of Reflective Memory real-time network products. The other members of the family are , PCI mezzanine card (PMC), and VMIPCI-5565, the PCI-compatible board. All three of these products are network compatible, and may be integrated into a network in any combination. This family of products allows computers, workstations, PLCs, and other embedded controllers with dissimilar operating systems, or no operating system at all, to share data in real time. To the local node, the Reflective Memory board appears as shared memory. Data can be written to or read from the memory by any level of software, including the application itself. Data written to the Reflective Memory in one node is transported by the network hardware to all other nodes, and placed in the same address on those node’s Reflective Memory boards. This transport of data is accomplished without the involvement of the processors on any node. Using this system, all nodes on the network have a local copy of shared data available for immediate access. Product Overview: The Reflective Memory concept provides a very fast and efficient way of sharing data across distributed computer systems. GE Fanuc Embedded Systems’ Reflective Memory interface allows data to be shared between up to 256 independent systems (nodes) at rates up to 174 Mbyte/s. Each Reflective Memory board can be configured with either 64 Mbyte or 128 Mbyte of onboard SDRAM. The local SDRAM provides fast Read access times to stored data. Writes are stored in local SDRAM and broadcast over a high speed fiber optic data path to other Reflective Memory nodes. The transfer of data between nodes is software transparent, so no I/O overhead is required. Transmit and Receive FIFOs buffer data during peak data rates to optimize processor and bus performance to maintain high data throughput. The Reflective Memory also allows interrupts to one or more nodes by writing to a byte register. These interrupt (four levels, each user definable) signals may be used to synchronize a system process, or used to follow any data. The interrupt always follows the data to ensure the reception of the data before the interrupt is acknowledged. Each node on the system has a unique identification number between 0 and 255. The node number is established during hardware system integration by a series of onboard switches. This node number can be read by software by accessing an onboard register. In some applications, this node number would be useful in establishing the function of the node. Link Arbitration: The system is a fiber-optic daisy chain ring as shown in Figure 1. Each transfer is passed from node-to-node until it has gone all the way around the ring and reaches the originating node. Each node retransmits all transfers that it receives except those that it originated. Nodes are allowed to insert transfers between transfers passing through. Interrupt Transfers: The provides four network interrupts. Any processor can generate an interrupt on any other node on the network. In addition, any processor can generate an interrupt on all nodes on the network with a single register write. In response to this interrupt register write, the sending issues a special packet over the network, which contains the command strobe, the sender node ID, the destination node ID, and 32 bits of data. When a receiving node detects the proper combination of destination node ID and command strobe, it stores the sender note ID and the data in one of four 127 location-deep FIFOs. The four FIFOs correspond to the four interrupts. Upon storing this information in a FIFO, the receiving node issues an interrupt to the local processor if it has been software-enabled. The 32 bits of data stored in the FIFO is user-definable and typically is treated as an interrupt vector. As part of an interrupt service routine, the local processor reads this information out of the FIFO and acts accordingly | 
