TNA1-TU01-SH模块备件

TNA1-TU01-SH

对PCI9030 PCI基址寄存器编程后，软件必须启用
PCI9030，用于PCI9030PCI命令寄存器中的PCI I/O和/或PCI内存空间访问
（偏移量0x04）：
要启用对PCI9030的PCI I/O空间访问，请将位0设置为“1”。
要启用对PCI9030的PCI内存空间访问，请将位1设置为“1”。
TPMC815用户手册版本2.0.214页，共20页
5.2本地配置寄存器（LCR）
复位后，从板载串行总线加载PCI9030本地配置寄存器
EEPROM的配置。
PCI9030本地配置寄存器的PCI基址为：
PCI9030 PCI基址0（PCI内存空间映射）（PCI中的偏移量0x10
配置寄存器空间）
PCI9030 PCI基址1（PCI I/O空间映射）（PCI配置中的偏移量0x14
寄存器空间）
请勿更改PCI9030本地配置寄存器中的硬件相关位设置。
抵消
PCI基
住址
寄存器值
0x00本地地址空间0范围0x0FFF_FFF1
0x04本地地址空间1范围0x0FFF_FF00
0x08本地地址空间2范围0x0000_0000
0x0C本地地址空间3范围0x0000_0000
0x10本地扩展ROM范围0x0000_0000
0x14本地地址空间0重新映射0x0000_0001
0x18本地地址空间1重新映射0x0000_0001
0x1C本地地址空间2重新映射0x0000_0000
0x20本地地址空间3重新映射0x0000_0000
0x24本地表达式ROM重新映射0x0000_0000
0x28本地地址空间0描述符0x5401_E0
0x2C本地地址空间1描述符0x5401_E0
0x30本地地址空间2描述符0x0000_0000
0x34本地地址空间3描述符0x0000_0000
0x38本地扩展ROM描述符0x0000_0000
0x3C芯片选择0基址0x0000_0004
0x40芯片选择1基址0x0000_000C
0x44芯片选择2基址0x0000_0000
0x48芯片选择3基址0x0000_0000
0x4C中断控制/状态0x0041
0x4E EEPROM写保护边界0x0030
0x50杂项控制寄存器0x0078_0000
0x54通用I/O控制0x0224_9249
0x70 Hidden1电源管理0x0000_0000
0x74隐藏2电源管理0x0000_0000
表5-2:PCI9030本地配置寄存器
TPMC815用户手册版本2.0.215页，共20页
5.3 EEPROM的配置
通电或PCI复位后，PCI9030从板上加载初始配置寄存器数据
EEPROM的配置。
配置EEPROM包含以下配置数据：
 地址0x00至0x27:PCI9030 PCI配置寄存器值
 地址0x28至0x87:PCI9030本地配置寄存器值
 地址0x88至0xFF:Reserved00003
0x50 VPD数据Y 00000000
表5-1:PCI9030 PCI头
子系统ID:TPMC815-21R:0x0015
TPMC815用户手册版本2.0.213页，共20页
5.1.2 PCI基址初始化
PCI基址初始化是PCI主机软件的范围。
PCI9030 PCI基址初始化：
1.将0xFFFF_ FFFF写入PCI9030 PCI基址寄存器。
2.读回PCI9030 PCI基址寄存器。
3.对于PCI基址寄存器0:5，检查PCI地址空间的位0：
位0='0'需要PCI内存空间映射
位0='1'需要PCI I/O空间映射
对于PCI扩展ROM基址寄存器，检查位0的使用情况：
位0='0'：未使用扩展ROM
位0='1'：使用扩展ROM
4.对于PCI I/O空间映射，从位位置2开始，一个位集确定
所需的PCI I/O空间大小。
对于PCI内存空间映射，从位位置4开始，设置为“1”的一位确定大小
所需的PCI存储器空间大小。
对于PCI扩展ROM映射，从位位置11开始，设置为“1”的一位确定
所需的PCI扩展ROM大小。
例如，如果PCI基址寄存器的5位被检测为设置为“1”的一位，则
PCI9030正在请求32字节的空间（地址位4:0不是基址解码的一部分）。
5.确定基址并将基址写入PCI9030 PCI基址
登记对于PCI内存空间映射，映射的地址区域必须符合
PCI9030 PCI的位3:1定义TPMC815是标准的单宽32位PMC
模块具有完整的ARCNET接口，使用
控制器COM20020。COM20020包含
带收发器和双端口RAM的ARCNET控制器。
TPMC815-21R提供隔离的RS485
差分驱动器接口。
TPMC815-21R的大速度为5.0 Mbps。
该模块非常适合工业/工厂应用
自动化和汽车应用。
软件支持（TDRV007 SW xx）可用于：
不同的操作系统。
技术信息
 标准单宽32位PMC模块
根据IEEE P1386.1
 PCI 2.1兼容接口
 板尺寸：149毫米x 74毫米
 基于COM20020的ARCNET接口
完整的ARCNET控制器，带收发器和
双端口RAM
 工业/工厂自动化和自动化的理想选择
汽车应用
 确定性5Mbps令牌传递协议
 改进的诊断
 带on的隔离RS485差分驱动器接口
板

TNA1-TU01-SH

TNA1-TU01-SH

After programming the PCI9030 PCI Base Address Registers, software must enable the
PCI9030 for PCI I/O and/or PCI Memory Space access in the PCI9030 PCI Command Register
(Offset 0x04):
To enable PCI I/O Space access to the PCI9030, set bit 0 to '1'.
To enable PCI Memory Space access to the PCI9030, set bit 1 to '1'.
TPMC815 User Manual Issue 2.0.2 Page 14 of 20
5.2 Local Configuration Register (LCR)
After reset, the PCI9030 Local Configuration Registers are loaded from the on board serial
configuration EEPROM.
The PCI base address for the PCI9030 Local Configuration Registers is:
PCI9030 PCI Base Address 0 (PCI Memory Space mapped) (Offset 0x10 in the PCI
Configuration Register Space)
PCI9030 PCI Base Address 1 (PCI I/O Space mapped) (Offset 0x14 in the PCI Configuration
Register Space)
Do not change hardware dependent bit settings in the PCI9030 Local Configuration Registers.
Offset from
PCI Base
Address
Register Value
0x00 Local Address Space 0 Range 0x0FFF_FFF1
0x04 Local Address Space 1 Range 0x0FFF_FF00
0x08 Local Address Space 2 Range 0x0000_0000
0x0C Local Address Space 3 Range 0x0000_0000
0x10 Local Exp. ROM Range 0x0000_0000
0x14 Local Address Space 0 Remap 0x0000_0001
0x18 Local Address Space 1 Remap 0x0000_0001
0x1C Local Address Space 2 Remap 0x0000_0000
0x20 Local Address Space 3 Remap 0x0000_0000
0x24 Local Exp. ROM Remap 0x0000_0000
0x28 Local Address Space 0 Descriptor 0x5401_E0E0
0x2C Local Address Space 1 Descriptor 0x5401_E0E0
0x30 Local Address Space 2 Descriptor 0x0000_0000
0x34 Local Address Space 3 Descriptor 0x0000_0000
0x38 Local Exp. ROM Descriptor 0x0000_0000
0x3C Chip Select 0 Base Address 0x0000_0004
0x40 Chip Select 1 Base Address 0x0000_000C
0x44 Chip Select 2 Base Address 0x0000_0000
0x48 Chip Select 3 Base Address 0x0000_0000
0x4C Interrupt Control/Status 0x0041
0x4E EEPROM Write Protect Boundary 0x0030
0x50 Miscellaneous Control Register 0x0078_0000
0x54 General Purpose I/O Control 0x0224_9249
0x70 Hidden1 Power Management 0x0000_0000
0x74 Hidden 2 Power Management 0x0000_0000
Table 5-2 : PCI9030 Local Configuration Register
TPMC815 User Manual Issue 2.0.2 Page 15 of 20
5.3 Configuration EEPROM
After power-on or PCI reset the PCI9030 loads initial configuration register data from the on board
configuration EEPROM.
The configuration EEPROM contains the following configuration data:
 Address 0x00 to 0x27 : PCI9030 PCI Configuration Register Values
 Address 0x28 to 0x87 : PCI9030 Local Configuration Register Values
 Address 0x88 to 0xFF : Reserved0000 00 03
0x50 VPD Data Y 00000000
Table 5-1 : PCI9030 PCI Header
Subsystem-ID: TPMC815-21R: 0x0015
TPMC815 User Manual Issue 2.0.2 Page 13 of 20
5.1.2 PCI Base Address Initialization
PCI Base Address Initialization is scope of the PCI host software.
PCI9030 PCI Base Address Initialization:
1. Write 0xFFFF_FFFF to the PCI9030 PCI Base Address Register.
2. Read back the PCI9030 PCI Base Address Register.
3. For PCI Base Address Registers 0:5, check bit 0 for PCI Address Space:
Bit 0 = '0' requires PCI Memory Space mapping
Bit 0 = '1' requires PCI I/O Space mapping
For the PCI Expansion ROM Base Address Register, check bit 0 for usage:
Bit 0 = ‘0’: Expansion ROM not used
Bit 0 = ‘1’: Expansion ROM used
4. For PCI I/O Space mapping, starting at bit location 2, the first bit set determines the size of the
required PCI I/O space size.
For PCI Memory Space mapping, starting at bit location 4, the first bit set to '1' determines the size
of the required PCI Memory space size.
For PCI Expansion ROM mapping, starting at bit location 11, the first bit set to '1' determines the
required PCI Expansion ROM size.
For example, if bit 5 of a PCI Base Address Register is detected as the first bit set to ‘1’, the
PCI9030 is requesting a 32 byte space (address bits 4:0 are not part of base address decoding).
5. Determine the base address and write the base address to the PCI9030 PCI Base Address
Register. For PCI Memory Space mapping the mapped address region must comply with the
definition of bits 3:1 of the PCI9030 PCIThe TPMC815 is a standard single-width 32 bit PMC
module with a complete ARCNET interface using the
controller COM20020. The COM20020 contains the
ARCNET controller with transceiver and Dual Port RAM.
The TPMC815-21R provides an isolated RS485
differential driver interface.
The maximum speed of the TPMC815-21R is 5.0 Mbps.
The module is ideal suited for industrial / factory
automation and automotive applications.
Software support (TDRV007-SW-xx) is available for
different operating systems.
Technical Information
 Standard single-width 32 bit PMC module conforming
to IEEE P1386.1
 PCI 2.1 compliant interface
 Board size: 149 mm x 74 mm
 ARCNET Interface based on COM20020
Complete ARCNET controller with transceiver and
Dual Port RAM
 Ideal for industrial / factory automation and
automotive applications
 Deterministic 5 Mbps Token Passing Protocol
 Improved diagnostics
 Isolated RS485 differential driver interface with on
board DC/DC converter
 Operating Temperature Range -40°C to +85°C
TEWS TECHNOLOGIES GmbH keeps the right to change technical specification without further notice.
All trademarks mentioned are property of their respective owners.
Issue 2.0.2
2020-11-03
TEWS TECHNOLOGIES GmbH
Am Bahnhof 7 25469 Halstenbek, Germany
Phone: +49 (0) 4101 4058 0 Fax: +49 (0) 4101 4058 19
e-mail: info@tews.com www.tews.com
The Embedded I/O Company
Order Information
RoHS Compliant
TPMC815-21R ARCNET, COM20020, 5 Mbps, isolated RS485 Interface, DB9
For the availability of non-RoHS compliant (leaded solder) products please contact TEWS.
Documentation
TPMC815-DOC User Manual
Software
TDRV007-SW-25 Integrity Software Support
TDRV007-SW-42 VxWorks Software Support (Legacy and VxBus-Enabled Software Support)
TDRV007-SW-65 Windows Software Support
TDRV007-SW-82 Linux Software Support
TDRV007-SW-95 QNX Software Support
For other operating systems please contact TEWS