6205BZ10000H 125S2821-3 D/F 控制板用于驱动数据记录

6205BZ10000H 125S2821-3 D/F 控制板用于驱动数据记录 

反馈回路中的电阻器，以小化电阻器的寄生电容。
2.尽量减少电源引脚与高频旁路电容器之间的距离（小于0.25英寸）
高质量、100 pF至0.1µF、C0G和NPO型去耦电容器，额定电压至少为三
大于放大器大电源的倍，以确保存在低阻抗路径
放大器电源引脚跨放大器增益带宽规格。在设备引脚处，执行
不允许接地和电源平面布局靠近信号I/O引脚。避窄
电源和接地迹线，以小化引脚和去耦电容器之间的电感。这个
电源连接必须始终与这些电容器去耦。更大（2.2-µF至6.8-µF）
在较低频率下有效的去耦电容器必须用于电源引脚。这些被放置
并且在PC板的相同区域中的多个设备之间共享。
3.仔细选择和放置外部组件，以保持高频性能
使用低电抗电阻器。表面贴装电阻器工作佳，整体更紧密
布局切勿在高频应用中使用线绕电阻器。因为输出引脚和反相
输入引脚对寄生电容敏感，始终定位反馈和串联输出
电阻器（如有）尽可能靠近输出引脚。放置其他网络组件（如非反相
输入端接电阻器）。即使在低寄生电容分流外部
电阻器，高电阻值会产生显著的时间常数，从而降低性能。什么时候
将OPA858配置为电压放大器，使电阻值尽可能低并与
负载驱动注意事项。减小电阻器值可保持电阻器噪声项较低，并将其小化
寄生电容的影响。然而，较低的电阻值会增加动态功率
因为RF和RG成为放大器输出负载网络的一部分。
12.2布局示例
图64.布局建议
偏置电压
穿越火线
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产品文件夹链接：OPA858
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布局示例（续）
将OPA858配置为跨阻抗放大器时，必须格外小心，以尽量减少
雪崩光电二极管（APD）和放大器之间的电感。始终将光电二极管置于
PCB与放大器的同一侧。将放大器和APD放置在PCB的相对侧
增加了通孔电感引起的寄生效应。APD包装可能相当大，通常需要
将APD放置得比理想的离放大器更远。两个设备之间的附加距离会导致：
如图65所示，APD和运算放大器反馈网络之间的电感增加
电感不利于失补偿放大器的稳定性，因为它将APD电容与
噪声增益传递函数。噪声增益由等式4给出。在
反馈网络增加等式4中的分母，从而降低噪声增益和相位
边缘如果在TO can中使用带引线的APD，则应通过切割
TO的引线应尽可能短。
图65所示的布局可以改进

6205BZ10000H 125S2821-3 D/F 控制板用于驱动数据记录 

6205BZ10000H 125S2821-3 D/F 控制板用于驱动数据记录 

resistor in the feedback loop to minimize the parasitic capacitance from the resistor.
2. Minimize the distance (less than 0.25") from the power-supply pins to high-frequency bypass capacitors. Use
high quality, 100-pF to 0.1-µF, C0G and NPO-type decoupling capacitors with voltage ratings at least three
times greater than the amplifiers maximum power supplies to ensure that there is a low-impedance path to
the amplifiers power-supply pins across the amplifiers gain bandwidth specification. At the device pins, do
not allow the ground and power plane layout to be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between the pins and the decoupling capacitors. The
power-supply connections must always be decoupled with these capacitors. Larger (2.2-µF to 6.8-µF)
decoupling capacitors, effective at lower frequency, must be used on the supply pins. These are placed
further from the device and are shared among several devices in the same area of the PC board.
3. Careful selection and placement of external components preserves the high-frequency performance
of the OPA858 . Use low-reactance resistors. Surface-mount resistors work best and allow a tighter overall
layout. Never use wirewound resistors in a high-frequency application. Because the output pin and inverting
input pin are the most sensitive to parasitic capacitance, always position the feedback and series output
resistor, if any, as close to the output pin as possible. Place other network components (such as noninverting
input termination resistors) close to the package. Even with a low parasitic capacitance shunting the external
resistors, high resistor values create significant time constants that can degrade performance. When
configuring the OPA858 as a voltage amplifier, keep resistor values as low as possible and consistent with
load driving considerations. Decreasing the resistor values keeps the resistor noise terms low and minimizes
the effect of the parasitic capacitance. However, lower resistor values increase the dynamic power
consumption because RF and RG become part of the output load network of the amplifier.
12.2 Layout Example
Figure 64. Layout Recommendation
Vbias
CF
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Layout Example (continued)
When configuring the OPA858 as a transimpedance amplifier additional care must be taken to minimize the
inductance between the avalanche photodiode (APD) and the amplifier. Always place the photodiode on the
same side of the PCB as the amplifier. Placing the amplifier and the APD on opposite sides of the PCB
increases the parasitic effects due to via inductance. APD packaging can be quite large which often requires the
APD to be placed further away from the amplifier than ideal. The added distance between the two device results
in increased inductance between the APD and op amp feedback network as shown in Figure 65. The added
inductance is detrimental to a decompensated amplifiers stability since it isolates the APD capacitance from the
noise gain transfer function. The noise gain is given by Equation 4. The added PCB trace inductance between
the feedback network increases the denominator in Equation 4 thereby reducing the noise gain and the phase
margin. In cases where a leaded APD in a TO can is used inductance should be further minimized by cutting the
leads of the TO can as short as possible.
The layout shown in Figure 65 can be improve