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SAFT103CON 57777290 控制板印刷电路卡

型号: SAFT103CON 57777290  分类: foxboro
  • SAFT103CON 57777290
  • SAFT103CON 57777290
  • SAFT103CON 57777290
  • SAFT103CON 57777290
  • SAFT103CON 57777290


SAFT103CON 57777290 控制板印刷电路卡 SAFT103CON 57777290 控制板印刷电路卡 SAFT103CON 57777290 控制板印刷电路卡 SAFT103CON 57777290 控制板印刷电路卡
















SAFT103CON 57777290 控制板印刷电路卡 
CU数据链路和RCU控制链路。
RCU数据链路是用于传输数据的快速通信信道
需要保持备份CPU与主CPU同步。
数据链路采用TK855 RCU数据链路电缆。
RCU控制链路用于角色选择和CPU标识分配
(上/下)。
TK856 RCU控制链路电缆用于控制链路。
容错原则
冗余处理器单元的容错原理基于:
将备份单元持续更新到与主单元相同的状态。这
使备份单元能够在不影响周围系统的情况下进行控制
无障碍的方式。
这一原则涉及程序执行的动态划分
单元和创建处理器单元状态为的回滚点
完全定义。
在此上下文中,处理器单元的总状态定义为处理器单元的
内部状态,即处理器寄存器的内容,加上
数据存储器。
每次主单元通过回滚时,备份单元的状态都会更新
点,使备份单元能够从上次回滚恢复程序执行
如果主单元由于错误而失败,则通过点。
为了尽量减少更新中涉及的信息量,备份
只有在新回滚点之后发生更改时,才会更新单元。
在回滚点之间,这些写入数据内存的更改存储在
备份单元中的日志缓冲区。在回滚点,处理器的总寄存器
内容也被写入数据存储器,因此该信息也
登录。一旦建立了回滚点,记录的写操作包括
传输到备份单元的数据存储器。
1节介绍PM891/PM86x/TP830处理器单元-冗余
3BSE036351-510 A 49
如果主单元由于错误而失败,备份单元将从
后一个回滚点,这意味着后一个执行单元部分重新执行
通过备份单元。为了重新执行执行单元的一部分
影响外围设备(CEX总线上的通信设备),外围设备
单位的引用也记录在回滚点之间。在重新执行期间
已执行的外围设备参考结果如下
而不是重新执行它们。检索读取操作的结果
从日志中,写入操作在不执行的情况下通过,因为它们已经
已被处决。因此,外围设备的状态不受重新执行的任何影响,但发生的时间延迟除外。
处理器单元中包含的RAM提供自动双反转
用于检测存储器中任意位错误的存储器功能。
•所有内存更新都写入主内存和反转内存
并行存储器。
•在每个存储器读取周期,比较两个存储器的数据。
•如果数据不匹配,则强制转换。
双反转内存处理在硬件中完成,没有任何延迟
存储器循环时间。
冗余配置中的MAC和IP地址处理
SAFT103CON 57777290 控制板印刷电路卡 
SAFT103CON 57777290 控制板印刷电路卡

SAFT103CON 57777290 控制板印刷电路卡 
Cu data link and RCU control link.
RCU data link is a fast communication channel used to transmit data
It is necessary to keep the backup CPU synchronized with the main CPU.
TK855 RCU data link cable is used for data link.
RCU control link is used for role selection and CPU identification assignment
(up / down).
Tk856 RCU control link cable is used for control link.
Fault tolerance principle
The fault tolerance principle of the redundant processor unit is based on:
The backup unit is continuously updated to the same state as the primary unit. this
So that the backup unit can control without affecting the surrounding system
Accessibility.
This principle involves the dynamic division of program execution
Unit and create rollback point with processor unit status
Completely defined.
In this context, the overall state of the processor unit is defined as the
Internal status, i.e. the contents of the processor register, plus
Data storage.
Every time the primary unit passes the rollback, the status of the backup unit is updated
Point to enable the backup unit to recover program execution from the last rollback
If the master unit fails due to an error, pass through the point.
In order to minimize the amount of information involved in the update, backup
Cells are updated only when changes occur after the latest rollback point.
Between rollback points, these changes written to the data memory are stored in
Log buffer in the backup unit. At the rollback point, the total register of the processor
The content is also written into the data memory, so the information is also
Sign in. Once the rollback point is established, the recorded write operations include
To the data storage of the backup unit.
Section 1 describes the pm891 / pm86x / tp830 processor unit - redundancy
3BSE036351-510 A 49
If the primary unit fails due to an error, the backup unit will
The last rollback point, which means that the last execution unit is partially re executed
Through the backup unit. To re execute part of the execution unit
Affect peripheral devices (communication devices on CEX bus), peripheral devices
References to units are also recorded between rollback points. During re execution
The peripheral reference results that have been executed are as follows:
Rather than re executing them. Retrieve the results of the read operation
From the log, write operations pass without execution because they have
I have been executed. Therefore, the state of the peripheral device is not affected by any re execution, except for the time delay that occurs.
The ram included in the processor unit provides automatic double inversion
A memory function for detecting an arbitrary bit error in memory.
• all memory updates are written to main memory and reverse memory
Parallel memory.
• compare the data of the two memories in each memory read cycle.
• force conversion if the data does not match.
Double inversion memory processing is completed in hardware without any delay
Memory cycle time.
Mac and IP address handling in redundant configuration

SAFT103CON 57777290 控制板印刷电路卡 

 硬盘继电器单元 RD086-16L/B 58038776



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